Price: $3,999.00
Length: 4 Days
MIPI Technical Crash Course Description
MIPI Technical Crash Course, Mobile Industry Processor Interface, is a 4-day technical training bootcamp. Learn how MIPI technology will work on mobile devices, smartphones, wireless-enabled tablets, netbooks and future user equipment Learn distinctive requirements of mobile terminals by understanding MIPI Specifications on hardware and software in mobile devices. MIPI Technical Crash Course covers all hardware aspects, processor or system-on-a-chip, ports or buses, interface to a variety of peripherals such as displays, touch screen, cameras, memory, IoT, VR/AR, Autonomous driving, communications devices, and interconnections among the peripheral devices. MIPI Technical Crash Course looks at the interface technology, such as signaling characteristics and protocols applied to MIPI interfaces applicable to products used in different network technologies, including GSM, UMTS, LTE, LTE-Advanced, LTE-Advance Pro, 5G NR and more.
MIPI Alliance specifications serve six fundamental application areas:
- Physical layer applications: A family of high-speed physical layers to serve essential interconnection needs in a device
- Multimedia applications: Protocols for cameras and imaging, displays, touch, and audio
- Chip-to-chip/IPC applications: Protocol layers for chip-to-chip or interprocessor communications (IPC)
- Control and data applications: Protocol layers to manage lower-speed components
- Debug and trace applications: Tools for debugging embedded systems throughout the development life cycle
- Software integration applications: Tools that streamline software integration of components in mobile-connected devices
Learning Objectives
Upon completion of this course, the attendees will learn:
- Concepts behind MIPI Interfaces in a Mobile Platform
- Reasons for MIPI as an Open Industry-standard Layered Protocol
- MIPI Layer Protocols
- MIPI Physical Layer
- How D-PHY and M-PHY work
- Overview of D-PHY
- Overview of M-PHY
- Overview of C-PHY
- Basics operations of multimedia interfaces: CSI and DSI
- Overview of CSI-2 and CSI-3
- Overview of UniPro stack
- Basic operations of Low-Speed Multipoint Link (LML) and Serial Low-power Inter-chip Media Bus (SLIMbus®)
- Basic operations of Battery and camera Interfaces
- Overview of RF Front End
- How DigRF is used to connect to RF devices
- Basics of Low Latency Interface (LLI) Interconnect
- Basic of High-speed Synchronous Serial Interface (HSI)
- MIPI System Power Management Interface
- MIPI Interoperability and Conformance Testing
- MIPI Debug Architecture
- MIPI Standard Debug Interfaces
- MIPI System Trace Protocol
- MIPI Software Architecture
- MIPI Implementation Case Study: UFS, M-PHY and Unirpo
- MIPI Verification and Validation
- MIPI vulnerabilities and weaknesses
- MIPI cyber security issues and mitigtion techniques
Course Modules (Can be Customized)
Introduction to MIPI
- What is MIPI?
- Overview of MIPI Technology
- Scope and Benefits of MIPI
- System Design Specifications
- Overview of MIPI Specifications’
Current Application Areas
- Mobile Devices
- IoT (Internet of Things)
- Augmented/Virtual Reality
- Automotive
- MIPI specifications and applications for safety, infotainment, advanced driver assistance and autonomous cars (ADAS)
MIPI Specifications (Updated)
- Software Integration
- Debug and Trace
- Control and Data
- Audio
- Camera and Imaging
- Display and Touch
- Chip-to-Chip/IPC
- Physical Layers
Battery Interface Technology
- Technical Overview of Battery Interface (BIF)
- Scope of Specification
- Implementation Technologies
- Testing
- Practical Knowledge and Best Practices
Camera Interface Technology
- What is Camera Serial Interface (CSI)?
- Overview of CSI-2
- Overview of CSI-3
- Transmitter and Receiver Interface
- Camera Parallel Interface (CPI)
Debug and Trace
- MIPI Debug Architecture
- System Trace Protocol Specification
- Open System Trace (OST) Base Protocol Specification
- Parallel Trace Interface Specification
- Trace Wrapper Protocol Specification
- System Trace Protocol (STP)
DigRF Technology
- Overview of Radio Frequency Interface Technology in Mobile Devices
- DigRF and RFFE Specifications
- DigRF 3G, a baseband IC to RF IC interface standard for dual mode 2.5G/3.5G/4G
- DigRF 3G
- DigRF v4
- DigRF Baseband / RF Digital Interface Specification
- Logical, Electrical and Timing Characteristics – EGRPS Version
- Dual mode 3GPP 2.5G/3.5G mobile terminals
- MIPI Alliance Specification for Dual Mode 2.5G/3G Baseband/RFIC Interface
- Baseband ICs (BBICs) and Radio Frequency ICs (RFICs) in a single terminal
- M-PHY
- PHY Adaptation Layer
- DigRF Protocol
- Protocol Extensions
- Interface and Data Flow Control
- RF Control Model
- Radio API
- Modem Layer 1 SW
Display Interface Technology
- What is Display Serial Interface (DSI)?
- Display Interface Specifications
- Electrical Characteristics
- Timing Characteristics
- Pixel formats (mapping of pixel bits to data signals) Characteristics
- Display Command Set
- Display Pixel Interface DPI-2
- Display Bus Interface DBI-2
- Legacy Display Bus Interface
- Legacy Display
- Pixel Interface
- Stereoscope Display Formats
- Display Command Set (DCS)
- Command set to control display behaviors
High-speed Synchronous Serial Interface (HSI) Technology
- What is High Speed Synchronous Interface (HSI)?
- HSI physical layer
- Serial link efficiency
- Pin-count reduction
- Low Latency Interface Technology
Low Latency Interface (LLI) Specification
- Low Latency Interface v1.0.
- Architectural Overview
- Low Latency Interface (LLI) as a point-to-point interconnect
- Using memory mapped transactions
- Dedicated Low Latency traffic class (LL TC)
- LLI Stack
Peripheral and Interconnect Low-level Framework
- Peripheral and Interconnect Low-level Framework Specifications
- The Device Descriptor Block specification
- Services to transfer descriptor and configuration data between Devices on a MIPI Interconnect
- This specification is used with other MIPI Alliance specifications as part of a complete system design
- DDB Data
- DDB Levels
MIPI Physical Layer
- Physical Layer Specifications
- Specification of the PHY-Protocol Interface
- Interfaces for display, camera, audio, video, memory, power management and communication between Baseband to RFIC
- D-PHY Specification
- M-PHY Specification
- C-PHY Specification
RF Front End
- RF Front-End Specification
- Overview of Mobile phone radios
- RF Front-End Control Interface (RFFE)
- Power Amplifiers (PA)
- Low-Noise Amplifiers (LNA)
- Filters, switches, power management modules, antenna tuners and sensors
- RFFE Protocol Implementation Conformance Statement (PICS) for MIPI Alliance Specification
Serial Low-power Inter-chip Media Bus (SLIMbus®) Technology
- Serial Low-power Inter-chip Media Bus (SLIMbus®) Specification
- Scope of SLIMbus in a Mobile System
- SLIMbus Features
- Audio, data, bus and Device control on a single bus
System Power Management Interface Technology
- System Power Management Interface (SPMI) specification
- Control connectivity such as power management ICs
- Priority management by traffic classes
- Command acknowledgement supported in SPMI v2.0
- Low-level protocol, communication sequences and arbitration processes of the interface
- Example SPMI System Configuration
UniPro Technology
- UniPro Specifications
- Target applications for UniPro include wireless handsets, tablets/netbooks, digital cameras and multimedia devices
- Corresponding formal reference model (SDL) document (MIPI02)
- Specification and Description Language (SDL)
- SDL State Machines for formal definition of PHY Adapter for M-PHY (L1.5)
- Data Link (L2)
- Network (L3)
- Transport (L4)
- Layer protocols and Device Management Entity (DME)
- Data structures, such as Packets and Frames
- The PHY Adapter, Data Link, Network and Transport layer protocols
- SDL Document
MIPI Security
- MIPI Interfaces
- Vulnerabilities and weaknesses
- Needs and strategies for addressing security in MIPI Alliance interface specifications
- Adversaries that need to be mitigated against and the threat models
- Discussions and Case Studies
MIPI Workshop (Hands-on)
- Integration across the hardware and software stack
- Hardware Abstraction Libraries (HAL)
Memory management - Process management
- Networking
- User space C/C++ library layer
- Porting Android to MIPI Devices
- MIPI CSI and DSI Interfaces
- Analyzing, modeling and writing a CSI device driver
- Analyzing, modeling and writing a DSI device driver
Current MIPI Specifications
- Audio
- MIPI SLIMbus® v2.0 MIPI SoundWire® v1
- Camera and Imaging
- MIPI CSI-2℠ v2.0, MIPI Camera Serial Interface 2 MIPI CSI-3℠ v1.1, MIPI Camera Serial Interface 3 MIPI CPI℠ v1.0, MIPI Camera Parallel Interface MIPI CSI℠ v1.0, MIPI Camera Serial Interface
- Chip-to-Chip/IPC
- MIPI DigRF℠ v4 v1.2 MIPI Dual Mode℠ 2.5G / 3G RFIC v3.09.06 MIPI LLI℠ v2.1, MIPI Low Latency Interface MIPI UniPro℠ v1.61
- Control and Data
- MIPI BIF℠ v1.1.1, MIPI Battery Interface MIPI BIF℠ Hardware Abstraction Layer v1.0 MIPI eTrak℠ v1.1, MIPI Envelope Tracking Interface MIPI I3C℠ v1.0, MIPI Improved Inter Integrated Circuit MIPI RFFE℠ v2.0, MIPI RF Front-End Control Interface MIPI SPMI℠ v2.0, MIPI System Power Management
- Debug and Trace
- Audio MIPI SLIMbus® v2.0 MIPI SoundWire® v1
- Camera and Imaging MIPI CSI-2℠ v2.0, MIPI Camera Serial Interface 2 MIPI CSI-3℠ v1.1, MIPI Camera Serial Interface 3 MIPI CPI℠ v1.0, MIPI Camera Parallel Interface MIPI CSI℠ v1.0, MIPI Camera Serial Interface
- Chip-to-Chip/IPC MIPI DigRF℠ v4 v1.2 MIPI Dual Mode℠ 2.5G / 3G RFIC v3.09.06 MIPI LLI℠ v2.1, MIPI Low Latency Interface MIPI UniPro℠ v1.61
- Control and Data MIPI BIF℠ v1.1.1, MIPI Battery Interface MIPI BIF℠ Hardware Abstraction Layer v1.0 MIPI eTrak℠ v1.1, MIPI Envelope Tracking Interface MIPI I3C℠ v1.0, MIPI Improved Inter Integrated Circuit MIPI RFFE℠ v2.0, MIPI RF Front-End Control Interface MIPI SPMI℠ v2.0, MIPI System Power Management
- Display and Touch
- MIPI DBI℠ v1.0, MIPI Display Bus Interface
- MIPI DBI-2℠, MIPI Display Bus Interface 2
- MIPI DCS℠ v1.3, MIPI Display Command Set
- MIPI DPI-2℠ v2.00, MIPI Display Pixel Interface 2
- MIPI DPI℠ v1.0, MIPI Display Pixel Interface
- MIPI DSI-2℠ v1.0, MIPI Display Serial Interface 2
- MIPI DSI℠ v1.3.1, MIPI Display Serial Interface MIPI SDF℠ v1.0, MIPI Stereoscopic Display Formats
- Software Integration
- MIPI DDB℠ v1.0, MIPI Device Descriptor Block
- MIPI DisCo℠ v1.0, MIPI Discovery and Configuration (DisCo) Specification
Who Should Attend
Software Engineers, Hardware Engineers, Designers, Embedded software , Testing Engineers and Technical Managers who need to understand the details of MIPI interfaces.
Outline
Overview of MIPI
- Important MIPI Interfaces
- D-PHY
- M-PHY
- Unipro
- CSI-2
- CSI-3
- DSI
- JEDEC's UFS
MIPI PHY Layer
- Scope and Purpose of D-PHY and M-PHY
- Overview of D-PHY
- D-PHY Architecture and operation
- Overview of M-PHY
- M-PHY Architecture and operation
- Comparison between D-PHY and M-PHY
- Medium, Data rates, Electrical Signaling, HS Cocking and Line Coding, and Power
System Power Management Interface (SPMI)
- SPMI Overview and Features
- Advanced Real-time Power Management Techniques
- Physical interface and Low-level protocol
- I/O structures/physical layer
- Communication sequences
- Arbitration processes of the interface
- Signal timing requirements
- Example SPMI system configuration
The Battery Interface (BIF)
- Scope and purpose of battery communication interface standard for mobile devices
- The fundamental requirement for a battery interface
- Battery Interface Specification Requirements
- Battery type
- Hardware interface
- Power control
Camera Interface Specifications
- Camera Serial Interface (CSI)
- Overview
- Scope and Purpose
- Camera Parallel Interface (CPI) Legacy
- Camera Serial Interface CSI-1 Legacy
- Camera Serial Interface CSI-2 Overview of CSI-2
- Camera Parallel Interface (CPI)
- The physical layer of CSI
- Signaling scheme called SubLVDS
- Camera Control Interface (CCI)
- CCI Tx and Rx Interface
- Overview of Camera Serial Interface CSI-3
- Conformance test suite
- Other Requirements
Display Serial Interface (DSI)
- Overview, Scope and Purpose
- D-PHY physical interface
- Display Command Set (DCS)
- Display commands and logical flow
- Display Pixel Interface (DPI)-2
- Stereoscope Display Formats
- Electrical
- Timing
- Display Bus Interface (DBI) v2.0
- DSI conformance test suite
High-speed Synchronous Serial Interface (HSI) Interface
- Scope and Purpose
- The physical layer of the HSI
- Transmitter and receiver model
Low Latency Interface (LLI)
- Architectural Overview
- Scope and Purpose
- LLI stack: Layer model
- Transaction fragments on PHY adapter layer PDUs
- Dedicated Low Latency traffic class (LL TC).
- Power management
- Transaction layer
- Data link layer
- M-PHY implementation
Serial Low-power Inter-chip Media Bus (SLIMbus®)
- Introduction to SLIMbus
- Scope and Purpose
- SLIMbus Features
- Audio, data, bus and Device control on a single bus
- Physical layer
- Dynamic clock frequency
- Frame structure
- Message protocol and tracking
- Transport protocols
- Device classes
- Test suites
DigRF Interface
- Overview and Scope
- Electrical, logical and protocol aspects of the interface
- Programming model and physical interface between the BBICs and RFICs
- Physical layer based on M-PHY
- 8b/10b control character mapping
- DigRF 3G
- Dual-mode 3GPP 3G / 2.5G (UMTS/EGPRS) mobile terminals
- DigRF v4
- Long Term Evolution (LTE), LTE Advance and Mobile WiMAX
- Support for existing 3GPP standards such as 2.5G and 3.5G (EGPRS, UMTS, HSPA/HSPA+
- Large data rate and scalability to cover other non 3GPP air interfaces (Bluetooth, Zigbee, 802.11n/802.11ac, etc)
- Interface between one or more Baseband ICs (BBICs) and Radio Frequency ICs (RFICs)
RF Front-End Control Interface (RFFE)
- Introduction to RFFE
- Scope and Purpose
- Controlling RF front-end devices
- Front-end devices applied: Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, antenna tuners and sensors. Two-wire, and serial interface
- Point-to-multipoint connectivity
- Operating states
- Protocol layer
- Physical layer
- Command sequences and Broadcast messages
Unipro
- Introduction
- Scope and Purpose
- Bandwidth, application agnostic, support for a network and forward compatibility
- Stack overview
- M-PHY v2.0 + UniPro v1.41
- Level 1 based on D-PHY or M-PHY
- SDL State Machines for formal definition of PHY Adapter for M-PHY (L1.5)
- Data Link (L2)
- Network (L3)
- Transport (L4)
- Unipro Case studies: CSI-3, UFS
- Layer protocols and Device Management Entity (DME)
- Test suites
MIPI Software Specifications
- Overview
- Scope and Purpose
- Device Descriptor Block (DDB)
- Descriptor and configuration data
- Levels of conformity: Level 1, Level 2, and Level 3
- Other Requirements
Debug Specifications (Formerly known as Test & Debug Specification)
- MIPI debug architecture
- System Trace Protocol (STP)
- Open System Trace (OST) Base Protocol
- Parallel Trace Interface (PTI)
- Trace Wrapper Protocol (TWP)
JEDEC's UFS Case Study: Details of the MIPI Implementation
- Universal Flash Storage (UFS)
- UFS Architecture Overview
- UFS Top level Architecture
- Application Layer
- UFS Device Manager
- Service Access Points
- UFS Transport Protocol Layer
- UFS Interconnect Layer
- UFS Topology
- UFS Interconnect (UIC) Layer
- UFS Physical Layer Signals
- MIPI UniPro
- MIPI UniPro Related Attributes
- UFS Transport Protocol (UTP) Layer
- UFS Application and Command Layer