Length: 2 Days
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Design FMEA Training Applied to Semiconductors Training by Tonex

Design FMEA Training Applied to Semiconductors is a 2-day training workshop that will help engineers and designer to apply D-FMEAs to semiconductors stages of development including Silicon IP, processor/SoC architecture, package and platform (firmware, memory, power, mechanical, peripheral interfaces).

Learning Objectives

  • What Design Failure Mode and Effects Analysis (DFMEA) is
  • Benefits of Design FMEA and the management of quality and reliability in semiconductor product design
  • FMEA to semiconductor design and manufacturing processes
  • How Design Failure Mode and Effects Analysis (DFMEA) is related to Failure Mode and Effects Analysis (FMEA) and Process Failure Mode and Effects Analysis (PFMEA) in semiconductor manufacturing
  • Design Failure Mode and Effects Analysis (DFMEA) process and tools
  • Learn about Design FMEA input and output including RPN, severity, occurrence, and detection rankings
  • Learn about Requirements, Potential Failure Modes, Effects of Failure and Severity Ranking, Causes, Prevention Controls, Occurrence and Class Column, Detection Controls, calculating the Risk Priority Number (RPN) and more
  • Select an Effective DFMEA Cross Functional Teams (CFTs) in your organization
  • Analyze your process and plan Cross Functional Teams (CFTs) activities and control
  • Plan Design Verification Plan & Report (DVP&R)
  • Map design reviews to FMEA Outputs

Audience

The DFMEA training is a 2-day course designed for:

  • Engineers, scientists, and managers involved with semiconductors design and manufacturing who need system level D-FMEA
  • Anyone new to FMEAs or P-FMEAs with no experience
  • Product design personnel
  • Reliability, testing, and quality team members
  • R&D personnel
  • Product and process assurance people
  • Assembly personnel

Design FMEA Training Hands-on and In-Class Activities

  • 3 Labs
  • 2 Workshops
  • 1 Group Activity

Learning Objectives

Upon completion of this seminar, the attendees are able to:

  • Explain the concept and the purpose of Failure Mode and Effects Analysis (FMEA)
  • Discuss the benefits, requirements, and goals of FMEA in semiconductors design and manufacturing processes
  • Decide when to use Design FMEA and when Process-FMEA
  • Discuss the steps and process of the FMEA
  • Define the Design FMEA scope
  • Conduct all the steps of Design FMEA
  • Conduct the ranking scales for Severity, Occurrence, and Detection
  • Choose the appropriate technology methods to use as supplement to their DFMEA action plan
  • Make the Design FMEA into an active document
  • Develop a Control plan based on Design FMEA
  • Determine corrective actions in order to develop a more correct FMEA

Course Outline:

Overview of FMEA and DFMEA/Design FMEA

  • Introduction to Failure Mode and Effects Analysis (FMEA)
  • Definition of FMEA
  • How FMEA works
  • Why and where using FMEA
  • System/Subsystem/component Design FMEA
  • Manufacturing and Assembly Process FMEA
  • Machinery and Equipment FMEA (Logistics Support)
  • Purpose of an FMEA
  • Identifying potential risks
  • Prioritizing the risks
  • Developing an action plan to reduce the risks

Design-FMEA vs. Process-FMEA

  • What is DFMEA?
  • What is PFMEA?
  • Difference between DFMEA and PFMEA?
  • When to use which?
  • Special features (critical and significant)
  • Cooperation on special features
  • Characteristics as inputs to PFMEA
  • Procedure
    • Step-by-step directions of a PFMEA
    • How to use the FMEA Analysis Worksheet
    • How to customize the Severity, Occurrence, and Detection Ranking Scales
  • Control Plan
  • Tips on Combo DFMEA and PFMEA

Principal Complementary Tools for DFMEA

  • Boundary Diagrams
  • Parameter Diagram (P-Diagram)
  • Interface Diagram
  • Ishikawa “Fishbone” Diagram
  • Fault Tree Analysis (FTA)
  • Characteristic Matrix C
  • Brainstorming

Principles of DFMEA/Design-FMEA applied in Semiconductors Industry 

  • D-FMEAs to semiconductors
  • Stages of development including Silicon IP, processor/SoC architecture, package and platform (firmware, memory, power, mechanical, peripheral interfaces)
  • Identifying potential or known failure modes
  • Corrective and preventive actions
  • Disciplined analysis of the product/system design
  • Design-based failure modes
  • Design FMEA steps and flow
  • Examples
  • How to use the DFMEA Scope Worksheet
  • Step-by-step directions of a Design FMEA
  • Failure Mode Avoidance FMA /FPA Failure Prevention Analysis
  • Team structure and rules for efficiency – cross functional teams
  • Control Plan
  • Tips on DFMEA applied to stages of semiconductors development

Design FMEA for Semiconductor Activity Workshop: FMEA methodology and implementation

  • Greater complexity and greater costs for semiconductor design and manufacturing
  • Semiconductors product design problem
  • Improving reliability engineering in product development based on design theory
  • Analysis of critical semiconductor manufacturing steps: deposition, photoresist, lithography, etch, ionization and packaging
  • Tools to extract product functions
  • FMEA production and creation

Case study: Using C-K design theory to improve the FMEA process

  • Systematic approaches to the development of FMEA
  • The 7-step FMEA approach (AIAG and VDA 2019)
  • Improving FMEA based on design theory
  • Limits of failure-effect-cause identification using brainstorming methodology
  • Combining creativity and robust analysis through design theory
  • Data collection process and data analysis
  • Brainstorming and identifying potential Failure Effects
  • Disusing and determining the Severity of the Effect
  • Analyzing and identifying Potential Cause(s) of the Failure Mode
  • Determining the Probability of Occurrence of the Failure Mode
  • Identifying Design Verifications techniques for the Causes
  • Determining the Probability of Non-Detection of the Failure Mode
  • Prioritizing risks based on Risk Priority Number (RPN)
  • Corrective and Preventive Actions
  • Techniques to prioritizing Actions Based on the RPN

 

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