Price: $1,799.00
Length: 2 Days
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Introduction to NVM Express, NVMe Training

Introduction to NVM Express, is a 2-day NVMe training covering Non-Volatile Memory Express (NVMe).

NVM Express (NVMe), Non-Volatile Memory Host Controller Interface Specification (NVMHCI) is a logical device interface specification for accessing non-volatile storage media attached via a PCI Express (PCIe) bus.

Learn about NVMe as a communications interface and transfer protocol developed specially for SSDs by a consortium of vendors including Intel, Samsung, Sandisk, Dell, and Seagate.

NVM Express (NVMe) is a protocol for the transport of data over different media and for optimized storage in NAND flash. Peripheral Component Interconnect Express (PCIe) is currently the most used transport medium. Other media, like NVMe over Fabrics, are currently being standardized. NVMe is optimized for NAND flash chips. The protocol provides a high-bandwidth and low-latency framework to the storage protocol, but with flash-specific improvements.

NVM Express® (NVMe™) is an optimized, high-performance scalable host controller interface designed to address the needs of Enterprise and Client systems that utilize PCI Express®-based solid-state storage.

Designed to move beyond the dark ages of hard disk drive technology, NVMe is built from the ground up for non-volatile memory (NVM) technologies. NVMe is designed to provide efficient access to storage devices built with non-volatile memory, from today’s NAND flash technology to future, high performing, persistent memory technologies.

There are several performance vectors that NVMe addresses, including bandwidth, IOPs, and latency.

Learning Objectives

Upon completion of this course, the attendees will be able to:

  • Review PCIe configuration
  • Illustrate how NVMe Host Controller works
  • Review NVMe Host Controller Interface model
  • Explain the steps for device initialization
  • Explain how command queues are set up and managed
  • Explain how host software learns that commands have been completed
  • List defined command sets and how they function
  • Explain error reporting structures
  • Explore power management options

Course Agenda

An Introduction to NVMe

  • Background
  • History
  • Components and Terminology
  • Basics of PCIe
  • PCIe Architecture and Requirements for NVMe
  • Link Initialization and Signal Training
  • Flow Control and Quality of Service
  • PCIe Error Detection/HandlingCurrent Versions
  • PCIe (PCI Express)
  • Overview and Background of PCIe
  • PCIe Architecture Overview
  • PCI Header
  • PCI Power Management Capabilities
  • PCI Express Capability

Basics of NVMe

  • Advanced Host Controller Interface (AHCI)
  • Comparison with AHCI
  • Operating system (OS) support
  • Software support
  • High-level comparison of AHCI and NVMe
  • NVMe Topology and Architecture
  • Submission, Completion, Admin, and I/O Queues
  • Controller Capabilities Registers
  • NVMe Admin and I/O Commands

NVMe Protocol

  • NVMe protocol options
  • Data Structures
  • Simple Command Set
  • ADMIN Commands
  • NVM I/O Commands
  • Data Structures
  • Submission Queue & Completion Queue Definition
  • Submission Queue Entry – Command Format
  • Physical Region Page Entry and List
  • Scatter Gather List (SGL)
  • Metadata Region (MR)
  • Completion Queue Entry
  • Controller Memory Buffer
  • Namespace List
  • Controller List
  • Fused Operations
  • Command Arbitration
  • The NVMe Management Interface (NVMe-MI)
  • Inventory
  • Configuration
  • Health Status Monitoring
  • Change Management
  • NVMe DIF/DIX support
  • Enhanced power management hint
  • Option to use no local memory
  • Option to use large local memory for SQs
  • Live firmware updates
  • Additional commands for setting up Namespaces (to use with Reservations)
  • Command set and NVMe devices
  • Submission and completion queues

NVMe Host-Controller Interface Overview

  • Queue Management
  • NVMe Commands
  • Command execution
  • Creation and management of Queues
  • Priority and Arbitration of commands
  • Asynchronous Event Notification
  • Addressing modes
  • Get/Set Features

NVMe Architecture

  • Controller Architecture
  • Command Submission and Completion Mechanism (Informative)
  • Queue Management
  • Interrupts
  • Controller Initialization and Shutdown Processing
  • Asynchronous Event Request Host Software Recommendations (Informative)
  • NVMe Qualified Names
  • Updating Controller Doorbell Registers using a Shadow Doorbell Buffer
  • Architecture components
  • Firmware updates
  • Controller registers
  • Power Management
  • Reservations

NVMe Features

  • Firmware Update Process
  • Metadata Handling
  • End-to-end Data Protection (Optional)
  • Power Management
  • Virtualization Enhancements (Optional)
  • Doorbell Stride for Software Emulation
  • Reservations (Optional)
  • Host Memory Buffer (Optional)
  • Replay Protected Memory Block (Optional)
  • Device Self-test Operations (Optional)
  • Namespace Management (Optional)
  • Boot Partitions (Optional)
  • Telemetry (Optional)
  • Sanitize Operations (Optional)

NVMe Testing

  • Test cases
  • Error reporting, Error Reporting Structures
  • Command and Queue Error Handling
  • Media and Data Error Handling
  • Memory Error Handling
  • Internal Controller Error Handling
  • Controller Fatal Status Condition Using Analyzers
  • Test Reports

 

 

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