Price: $1,699.00

Length: 2 Days
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TONEX introduces “Mobile PCI Express (M-PCIe) Architecture training course

Mobile PCI Express training course begins with an overview of basic PCIe, system architecture and continues with the introduction of MIPI M-PHY design and its application in Mobile PCI Ecpress, M-PCIe. This innovative training course provides a technical overview of Mobile PCI Express’s architecture, hardware, software, protocols and the value of MIPI M-PHY as the new physical layer.

mobile PCI Express Training

Example of topics covered:Mobile environment design requirements

  • PCI Express protocol overview
  • Applications of ultra-low power requirements
  • PCIe programming models
  • Challenges of driving PCIe’s high data rates
  • PCI Express power enhancements
  • Dynamic Power Allocation (DPA) controls
  • Power-saving L1 sub-statesPCI Express extensions into the ultra-low power world of mobile devices
  • PCIe power protocol, programming models, and designs to the mobile space
  • M-PCIe™ Engineering Change Notification (ECN)
  • Mobile design goals such as power management, performance, and  asymmetric Link widths
  • Benefits of M-PCIe for Low-Power PCI Express Designs
  • Changes in M-PCIe devices
  • Changes in upper PCIe protocol layers
  • Transaction Layer (TL)
  • Data Link Layer (DLL)
  • The PCIe PHYs M-PHYs
  • PIPE vs. RMMI
  • Logical PHY Layer (LPL) unique new logic for M-PCIe implementations
  • M-PCIe for Low-Power PCI
  • M-PHY design
  • M-PHY protocols
  • M-PHY electrical specification
  • M-PHY state machines
  • M-PCIe and M-PHY “gears” for signaling rates

Upon completion of this course, the attendees will learn:

  • An overview of  PCI Express (PCIe)
  • M-PCIe Architecture and Protocols
  • Role of MIPI’s physical layer, M-PHY as the essential ingredient to M-PCIe
  • RRAP and RRC protocol for Link initialization
  • M-PHY Architecture
  • M-PGY Electrical Characteristics
  • M-PHY Electrical Interconnect and OMC
  • M-PHY Tx and Rx state machines


Course Content

Overview of PCI Express Protocol

  • An Overview of the PCI Express Standard
  • PCI Bus History and Overview
  • PCI Challenges
  • Benefits of PCI Express
  • PCI Express Architecture
  • PCI Express Layered Architecture
  • Upper layers
  • Software Layer
  • Applications
  • Transaction layer
  • Data link layer
  • Physical layer
  • Hardware protocol summary
  • PHY Logical
  • PHY Electrical

The M-PHY Specification

  • M-PHY Architecture and Operation
  • Concepts behind PIN, LINE, LANE, SUB-LINK, LINK, and M-PORT
  • LINE States and Signaling Schemes
  • Line Coding
  • State Machines

M-PHY Electrical Characteristics

  • M-TX Characteristics
  • Common M-TX Parameters
  • HS-TX Characteristics
  • PWM-TX Characteristics
  • SYS-TX Characteristics
  • M-RX Characteristics
  • Common M-RX Characteristics
  • Common M-RX Parameters
  • HS-RX Characteristics
  • PWM-RX Characteristics
  • SYS-RX Characteristics
  • SQ-RX Characteristics
  • PIN Characteristics
  • Ground Shift


Electrical Interconnect and OMC

  • Line Characteristics
  • Interconnect S-parameters Extraction
  • Optical Media Converter (OMC)
  • Types of OMCs
  • Internal and External OMCs
  • Architecture and Operations of OMC
  • OMC Configuration








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